A TLS-Based Output Response Analyzer for BIST
نویسندگان
چکیده
Built-In Self-Testing (BIST) of very large scale integrated circuits (VLSI) mainly consists of two components – test pattern generator (TPG) and output response analyze (ORA). Hence, under BIST, each of the inserted bypass storage cell (bscs) needs two flip-flops. This paper presents a novel architecture for ORA. The advantages of such architecture are that most bscs need one instead of two flip-flops, leading to the less hardware overhead shown in the experimental results. Key-Words: VLSI, testing, BIST, TPG, ORA, bscs
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